The present invention is generally directed to nanoscale computing and memory circuits, and, more particularly, to the electrochemical modification of nanowires and junctions between nanowires to optimize their properties for electronic circuit applications.
Above-referenced application Ser. No. 09/280,225 discloses and claims the fabrication of the nanoscale defect-tolerant and configurable devices by forming nanoscale crossbars first, and then configuring the electronic properties of the devices at each cross-point or intersection. It has also been proposed to use configurable molecules between the cross lines to control the electronic properties; see also above-referenced application Ser. No. 09/282,048.
The above-referenced patent applications are directed to the formation of a configurable film at the cross-points, such as a switchable molecule, an example of which is rotaxane. Investigations continue to develop new and different ways of configuring the crossbars, in an effort to provide improved performance.
In accordance with the present invention, configurable circuits comprise arrays of cross-points of one layer of metal or semiconductive nanoscale lines, or wires, crossed by a second layer of metal or semiconductive nanoscale lines, or wires, with a configurable layer between the lines. Methods are provided for altering the thickness and/or properties of the wires and the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer.
Specifically, a method is provided for configuring nanoscale devices in a crossbar array of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor materials. The method comprises:
(a) forming the first layer of nanoscale lines on a substrate;
(b) forming a solid phase configurable layer on the first layer at least in areas where the nanoscale lines of the second layer are to cross the nanoscale lines of the first layer;
(c) forming the second layer of nanoscale lines on the configurable layer, crossing over the first layer of nanoscale lines; and
(d) changing a property of the lines and/or configurable layer by oxidation or reduction to thereby configure the nanoscale devices to form logic and/or memory circuits. Examples of properties that may be changed include thickness, electronic properties, such as conductivity (resistivity), barrier height, capacitance, band gap, etc.